Semiconductor device

ABSTRACT

A semiconductor device has: a semiconductor substrate as a base layer having a main surface; a plurality of wiring swellings formed so as to be linearly swollen on the main surface; and a plurality of plugs made of a conductive material formed so as to bury a part of a recess formed by being sandwiched by wiring swellings. Wiring swelling includes a wiring layer, an on-wiring stopper film as a wiring layer top face protective layer formed so as to cover the top face of wiring layer, and a side wall spacer covering a side face of wiring layer and a side face of on-wiring stopper film. The level of the top face of wiring swelling and that of the top face of plug are almost the same with respect to the main surface as a reference.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device havingplug-type contact holes formed in a self aligning manner and a method offabricating the same.

[0003] 2. Description of the Background Art

[0004] As an LSI (Large Scale Integrated circuit) becomes finer and itspacking density increases, positioning of extremely high accuracy isrequired for overlaying a circuit pattern only by photolithography.Under such circumstances, self-aligned contact etching lessens therequired overlay accuracy. Since the required overlay accuracy islessened by the self-aligned contact etching, design with the aim ofachieving a finer device can be realized. The technique related to theself-aligned contact etching is therefore important in development of asemiconductor device.

[0005] Referring to FIGS. 34 to 45, a method of fabricating asemiconductor device in accordance with the conventional technique willbe described.

[0006] By a known technique, an isolated insulating film 1 is formed onthe surface of a semiconductor substrate 2 except for active regions 21.On the top face of semiconductor substrate 2, a wiring layer 4 having anon-wiring insulating film 3 is formed by a known technique. On-wiringinsulating layer 3 is an insulating film intended to protect wiringlayer 4 at the time of performing self-aligned contact hole etching.FIG. 34 is a plan view showing a resultant of the process. FIG. 35 is across section taken on line XXXV-XXXV. As shown in FIG. 36, by CVD(Chemical Vapor Deposition) or the like, a nitride film 25 is formed onthe top face so as to cover wiring layer 4 and on-wiring insulating film3. Nitride film 25 is to serve as a side wall spacer 5 (refer to FIG.42) functioning as a stopper film when the self-aligned contact etchingis performed.

[0007] As shown in FIG. 37, an insulating interlayer 6 is formed so asto cover nitride film 25 by CVD or the like, and its top face isplanarized by CMP (Chemical Mechanical Polishing) or entire-faceetching.

[0008] Further, a resist film 9 is formed on insulating interlayer 6.When it is seen from above, the entire substrate is covered with resistfilm 9. As shown in FIG. 38, a photolithography pattern 7 is disposed inthe position of each active area 21 and exposure is performed. As aresult, resist film 9 is removed from only the positions in whichcontact holes are desired to be opened. Anisotropic dry etching isperformed by using resist film 9 as a mask to remove insulatinginterlayer 6. As a result, as shown in FIG. 39, contact holes 110 areformed where plugs are desired to be provided. In contact holes 110,since insulating interlayer 6 is removed, nitride film 25 is exposed.FIG. 40 is a cross section taken along line XL-XL of FIG. 39.

[0009] As shown in FIG. 41, residual resist film 9 is removed. In astate where there is no resist film 9, anisotropic dry etching isperformed on the entire face. As shown in FIG. 42, a part of nitridefilm 25 is removed to expose active area 21 on the bottom of contacthole 110. Since contact holes 110 are etched in a self-aligned manner,high accuracy control of positioning holes is unnecessary. Afterexposing active area 21, nitride film 25 partially remains as side wallspacers 5. Since a part of insulating interlayer 6 is also etched by theanisotropic dry etching, as shown in FIG. 42, the thickness ofinsulating interlayer 6 is slightly reduced. FIG. 43 is a plan viewshowing the state at this stage. FIG. 42 is a cross section taken alongline XLII-XLII of FIG. 43. As shown in FIGS. 42 and 43, side wall spacer5 and active area 21 of semiconductor substrate 2 are exposed on theinside of contact hole 110.

[0010] By CVD or the like, polysilicon or the like is applied so as tocover the entire top face. The polysilicon is the material of plugs 111to be formed. The surface is planarized by CMP, etch-back, or the like,thereby forming plugs 111 as shown in FIG. 44. As a result, plug 111 iselectrically connected to active area 21 exposed on the bottom ofcontact hole 110.

[0011] As shown in FIG. 45, a new insulating interlayer 106 is formed.On the top face of insulating interlayer 106, a next wiring layer can beformed.

[0012] By repeating such a process, a semiconductor device in which aplurality of wiring layers are stacked and connected via plugs in thevertical direction is obtained.

[0013] The semiconductor device according to the conventional techniqueas described above has, however, three problems which will be describedhereinbelow.

[0014] First Problem

[0015] A first problem is short-circuiting caused by deterioration inburying property of the insulating interlayer. As devices are becomingfiner in recent years, the interval between neighboring wiring layers 4in the same layer is becoming narrower. There is also a case such thatthe film thickness of on-wiring insulating film 3 and nitride film 25varies. Due to the factors, there is a problem such that the buryingproperty of burying a material between wiring layers 4 deteriorates evenwhen insulating interlayer 6 having high covering properties is used.Concrete deterioration in burying property is, for example, as shown inFIG. 46, the recesses cannot be buried completely due to cavities 33created in insulating interlayer 6 grown on the uneven surface ofnitride film 25. Since the cavity 33 is formed so as to extend in thedirection perpendicular to the drawing sheet of FIG. 46, when contactholes 110 (refer to FIG. 40) are filled with the material of plugs, thematerial of plugs may enter the cavities 33. In this case, there is aproblem such that one of plugs 111 and the other plug 111 neighboring tothe one of plugs 111 in the direction perpendicular to the drawing sheetof FIG. 46 are short-circuited via the plug material in the cavity 33.

[0016] Second Problem

[0017] A second problem is insufficient insulation. As shown in FIGS. 38to 43, since the etching process is performed twice to form the contactholes 110, the amount of removing nitride film 25 by etching tends to belarge. If nitride film 25 is removed excessively, there is the case suchthat nitride film 25 becomes too thin as side wall spacer 5 to protectwiring layer 4 from plug 111 on the side by insulation. When the filmthickness of on-wiring insulating film 3, side-wall spacer 5, andinsulating interlayer 6 and the etching rate at the time of forming theconnection hole 110 vary, the accuracy of the shape obtained finallydeteriorates cumulatively. Due to the factors, a case where theinsulation on wiring layer 4 is insufficient may occur.

[0018] Third Problem

[0019] A third problem is an increase in thickness. In the case offabricating the device in accordance with the conventional technique, asshown in FIG. 45, the layers including plug 11 formed by the series ofprocesses become thick. The thickness of a product finally obtained byrepeatedly forming such layers increases more conspicuously. Theincrease in thickness disturbs reduction in size of a product and makesit difficult to carry out wiring through the layers.

[0020] An object of the invention is to provide a semiconductor devicerealized while solving the three problems and a method of fabricatingthe same.

SUMMARY OF THE INVENTION

[0021] In order to achieve the object, according to an aspect of theinvention, a semiconductor device includes: a base layer having a mainsurface; a plurality of wiring swellings formed so as to be linearlyswollen on the main surface; and a plurality of plugs made of aconductive material formed so as to bury a part of a recess in planview, the recess formed on the main surface by being sandwiched by thewiring swellings. The wiring swelling includes a wiring layer, a wiringlayer top face protective layer formed so as to cover the top face ofthe wiring layer, and a side wall spacer covering a side face of thewiring layer and a side face of the wiring layer top face protectivelayer. The level of the top face of the wiring swelling and that of thetop face of the plug being almost the same with respect to the mainsurface as a reference. With the configuration, a fabrication method offorming a plug first and forming the insulating interlayer can beemployed. Thus, a problem of short circuit between plugs caused by acavity conventionally created in the insulating interlayer can besolved. Since the number of times the side wall spacer is subjected toetching decreases, insulation of the wiring layer by the side wallspacer can be performed more reliably. Further, the height of the plugis almost the same as that of the wiring swelling, so that the thicknessof the whole can be reduced.

[0022] In the invention, preferably, a plug arrangement area in which atleast three plugs are arranged in the direction intersecting the wiringswelling is provided. In the plug arrangement area, the level of the topface of the wiring swelling in a portion sandwiched by the plugs ishigher than that of the top face of the other portion in the wiringswelling. By adopting the configuration, the material of the plug isformed first on the entire face and a portion to become a plug and theother portion can be separately formed by using a photolithographicpattern covering the plug arrangement area. Thus, the fabrication isfacilitated and the device can be fabricated with high accuracy.

[0023] In the invention, preferably, a plug arrangement area in which atleast four plugs are arranged in the direction intersecting the wiringswelling is provided. The base layer is a semiconductor substrate partlyhaving an isolated insulating film in the main surface, and a plugdirectly connected only to the isolated insulating film in the baselayer is included in the plug arrangement area. Alternately, in theinvention, preferably, a plug arrangement area in which at least fourplugs are arranged in the direction intersecting the wiring swelling isprovided. The wiring swelling includes an insulating interlayer underthe wiring layer, the base layer includes a conductive area and anon-conductive area in plan view, and a plug directly connected only tothe non-conductive area in the base layer is included in the plugarrangement area.

[0024] In each of the configurations, a dummy plug exists. With theconfigurations, the fabricating method of applying the material of theplug first on the entire face and simultaneously forming the plug andthe dummy plug by using a photolithographic pattern covering the plugarrangement area including a portion in which no plug is necessary canbe employed. Thus, fabrication is facilitated and the device can befabricated with high accuracy. Because of the presence of the dummyplug, the top face can be easily planarized in a post process.

[0025] In order to achieve the object, according to another aspect ofthe invention, a semiconductor device includes: a base layer having amain surface; a plurality of wiring swellings formed so as to belinearly swollen on the main surface; and a plurality of plugs made of aconductive material formed so as to bury a part of a recess in planview, the recess formed on the main surface by being sandwiched by thewiring swellings. The wiring swelling includes a wiring layer, a wiringlayer top face protective layer formed so as to cover the top face ofthe wiring layer, and a side wall spacer covering a side face of thewiring layer and a side face of the wiring layer top face protectivelayer. A plug arrangement area in which at least three plugs arearranged in a direction intersecting the wiring swelling is provided.The level of the top face of the wiring swelling in the portionsandwiched by plugs in the plug arrangement area is higher than that ofthe top face of the other portion of the wiring swelling. With theconfiguration, a fabrication method of forming a plug first and formingthe insulating interlayer next can be employed. Thus, a problem of shortcircuit between plugs caused by a cavity conventionally created in theinsulating interlayer can be solved. Since the number of times the sidewall spacer is subjected to etching decreases, insulation of the wiringlayer by the side wall spacer can be performed more reliably.

[0026] In the invention, preferably, a plug arrangement area in which atleast four plugs are arranged in the direction intersecting the wiringswelling is provided. The base layer is a semiconductor substrate partlyhaving an isolated insulating film in the main surface, and a plugdirectly connected only to the isolated insulating film in the baselayer is included in the plug arrangement area. Alternately, in theinvention, preferably, a plug arrangement area in which at least fourplugs are arranged in the direction intersecting the wiring swelling isprovided. The wiring swelling includes an insulating interlayer underthe wiring layer, the base layer includes a conductive area and anon-conductive area in plan view, and a plug directly connected only tothe non-conductive area in the base layer is included in the plugarrangement area.

[0027] In each of the configurations, a dummy plug exists. With theconfigurations, the fabricating method of applying the material of theplug first on the entire face and simultaneously forming the plug andthe dummy plug by using a photolithographic pattern covering the plugarrangement area including a portion in which no plug is necessary canbe employed. Thus, fabrication is facilitated and the device can befabricated with high accuracy. Because of the presence of the dummyplug, the top face can be easily planarized in a post process.

[0028] In order to achieve the object, according to the invention, amethod of fabricating a semiconductor device includes: a wiring swellingforming step of forming a plurality of wiring swellings on a base layerhaving a main surface so as to be linearly swollen on the main surface;a conducting material filling step of filling a recess created in themain surface by being sandwiched by the wiring swellings with aconductive material so as to linearly bury the recess; and a plugforming step of removing the conductive material except for an areawhich becomes a plug. By adopting the method, since a plug is formedfirst and then the insulating interlayer is formed, a problem of shortcircuit between plugs caused by a cavity conventionally created in theinsulating interlayer can be solved. Since the number of times the sidewall spacer is subjected to etching decreases, insulation of the wiringlayer by the side wall spacer can be performed more reliably.

[0029] In the invention, preferably, the plug forming step includes: aresist applying step of forming a resist film on the entire top face ofthe wiring swelling and the conductive material; a resist patternforming step of forming a resist pattern by removing an unnecessaryportion from the resist film by a mask pattern covering a desired areain which a plug is to be formed; and a conductive material removing stepof removing the conductive material by using the resist pattern as amask. By employing the method, a plug can be formed easily with highaccuracy. A mask pattern obtained by reversing the conventional maskpattern can be used, so that acquisition of the mask pattern issimplified.

[0030] In the invention, preferably, the mask pattern has a patternshape covering at least three desired areas arranged in a directionintersecting the wiring swelling. By adopting the method, the maskpattern can be simplified, and a plug can be formed easily with highaccuracy.

[0031] In the invention, preferably, the mask pattern has a patternshape covering the four or more desired areas arranged in the directionintersecting the wiring swelling. By adopting the method, the maskpattern can be simplified, and a plug can be formed more easily withhigh accuracy. Since a plug and a dummy plug are simultaneously formed,the flatness of the surface when an insulating interlayer or the like isformed can be improved.

[0032] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033]FIG. 1 is a plan view in a first process of a method offabricating a semiconductor device according to a first embodiment ofthe invention;

[0034]FIG. 2 is a cross section taken along line II-II of FIG. 1;

[0035]FIG. 3 is a cross section in a second process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0036]FIG. 4 is a cross section in a third process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0037]FIG. 5 is a cross section in a fourth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0038]FIG. 6 is a cross section in a fifth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0039]FIG. 7 is a plan view in the fifth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0040]FIG. 8 is a plan view in a sixth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0041]FIG. 9 is a plan view in a seventh process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0042]FIG. 10 is a cross section taken along line X-X of FIG. 9;

[0043]FIG. 11 is a cross section in an eighth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0044]FIG. 12 is a cross section in a ninth process of the method offabricating the semiconductor device according to the first embodimentof the invention;

[0045]FIG. 13 is a plan view in a sixth process of a method offabricating a semiconductor device according to a second embodiment ofthe invention;

[0046]FIG. 14 is a plan view in a seventh process of the method offabricating the semiconductor device according to the second embodimentof the invention;

[0047]FIG. 15 is a cross section taken along line XV-XV of FIG. 14;

[0048]FIG. 16 is a plan view in an eighth process of the method offabricating the semiconductor device according to the second embodimentof the invention;

[0049]FIG. 17 is a cross section taken along line XVII-XVII of FIG. 16;

[0050]FIG. 18 is a cross section in a ninth process of the method offabricating the semiconductor device according to the second embodimentof the invention;

[0051]FIG. 19 is a plan view in a sixth process of a method offabricating a semiconductor device according to a third embodiment ofthe invention;

[0052]FIG. 20 is a plan view in a seventh process of the method offabricating the semiconductor device according to a third embodiment ofthe invention;

[0053]FIG. 21 is a cross section taken along line XXI-XXI of FIG. 20;

[0054]FIG. 22 is a plan view in an eighth process of the method offabricating the semiconductor device according to the third embodimentof the invention;

[0055]FIG. 23 is a cross section taken along line XXIII-XXIII of FIG.22;

[0056]FIG. 24 is a cross section in a ninth process of the method offabricating the semiconductor device according to the third embodimentof the invention;

[0057]FIG. 25 is a cross section in a first process of the method offabricating the semiconductor device according to a fourth embodiment ofthe invention;

[0058]FIG. 26 is a cross section in a second process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0059]FIG. 27 is a cross section in a third process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0060]FIG. 28 is a cross section in a fourth process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0061]FIG. 29 is a cross section in a fifth process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0062]FIG. 30 is a cross section in a sixth process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0063]FIG. 31 is a cross section in a seventh process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0064]FIG. 32 is a cross section in an eighth process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0065]FIG. 33 is a cross section in a ninth process of the method offabricating the semiconductor device according to the fourth embodimentof the invention;

[0066]FIG. 34 is a plan view in a first process of a method offabricating a semiconductor device according to a conventionaltechnique;

[0067]FIG. 35 is a cross section taken along line XXXV-XXXV of FIG. 34;

[0068]FIG. 36 is a cross section in a second process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0069]FIG. 37 is a cross section in a third process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0070]FIG. 38 is a plan view in a fourth process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0071]FIG. 39 is a plan view in a fifth process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0072]FIG. 40 is a cross section taken along line XL-XL of FIG. 39;

[0073]FIG. 41 is a cross section in a sixth process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0074]FIG. 42 is a cross section in a seventh process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0075]FIG. 43 is a plan view of the structure of FIG. 42;

[0076]FIG. 44 is a cross section in an eighth process of the method offabricating the semiconductor device according to the conventionaltechnique;

[0077]FIG. 45 is a cross section in a ninth process of the method offabricating the semiconductor device according to the conventionaltechnique; and

[0078]FIG. 46 is an explanatory diagram showing problems of thesemiconductor device according to the conventional technique.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] First Embodiment

[0080] Referring to FIGS. 1 to 12, a method of fabricating asemiconductor device according to a first embodiment of the inventionwill be described.

[0081] By a known technique, isolated insulating film 1 is formed in thesurface of semiconductor substrate 2 except for active areas 21. On thetop face of semiconductor substrate 2, wiring layer 4 covered with anon-wiring stopper film 13 is formed by a known technique. The on-wiringstopper film 13 has to be an insulating film having a sufficiently lowselectivity in CMP or etching as compared with a conductive layer 22(refer to FIG. 5) to be formed in a later process, that is, having anetching rate sufficiently lower than that of conductive layer 22. Ason-wiring stopper film 13, for example, a silicon nitride film can beused. In such a manner, the structure shown in FIGS. 1 and 2 isobtained. As shown in FIG. 3, by CVD or the like, nitride film 25 isformed on the top face so as to cover wiring layer 4 and on-wiringinsulating film 3.

[0082] As shown in FIG. 4, the entire face is subjected to anisotropicetching to remove nitride film 25 on the bottom of the recesses of FIG.3 and active area 21 is exposed, thereby forming contact hole 10. Sincecontact holes 10 are formed in a self aligned manner, the holes arenaturally formed without high accuracy position control. On the insideof connection hole 10, by making a part of nitride film 25 remain, sidewall spacer 5 is formed. Side wall spacer 5 has a shape of, not a simplevertical wall, but a shape having a slope toward the bottom of contacthole 10.

[0083] The linearly swollen portion formed as described above includingwiring layer 4, on-wiring stopper film 13, and side wall spacer 5 willbe called a “wiring swelling” 41 hereinbelow.

[0084] As shown in FIG. 5, conductive layer 22 is formed so as to coverthe entire face by CVD or the like. Conductive layer 22 is a layer whichwill become as plug 11 (refer to FIGS. 10 to 12) and is made of amaterial such as polysilicon or amorphous silicon.

[0085] As shown in FIG. 6, on-wiring stopper film 13 is used as astopper, and the entire face is subjected to CMP or dry etching. Theprocess is stopped when the top face of on-wiring stopper film 13 isexposed. As a result, the top face of on-wiring stopper film 13 and thatof the remaining portion of conductive layer 22 become almost flat andflush with each other. FIG. 7 is a plan view showing this state. FIG. 6is a cross section taken along line VI-VI of FIG. 7.

[0086] As shown in FIG. 8, a resist film 15 is formed on the entire topface. A photolithographic pattern 14a is overlaid on each active area 21and exposure is performed. Photolithographic pattern 14a used here issimilar to photolithographic pattern 7 (refer to FIG. 38) used in theconventional technique but is reversed. Consequently, with conventionalphotolithographic pattern 7, resist film 15 is removed only in theportion where a connection hole is desired to be formed, and the resistfilm 15 remains on the other portion. In the embodiment, on thecontrary, resist film 15 remains only in the portion where a connectionhole is desired to be formed, and the resist film 15 on the otherportion is removed. Further, while using resist film 15 as a mask, dryetching is performed, and conductive layer 22 is removed in aplug-unnecessary portion 16. Only the portion under resist film 15 ofconductive layer 22 remains and serves as plug 11. FIG. 9 is a plan viewshowing the state. FIG. 10 is a cross section taken along line X-X ofFIG. 9. On-wiring stopper film 13, side wall spacer 5, and isolatedinsulating film 1 around the plug-unnecessary portion 16 are slightlyremoved from their surfaces. As described above, the material has anetching rate sufficiently lower than that of conductive layer 22, sothat its removal amount does not become an issue. By setting etchingtime to be slightly long, conductive layer 22 can be therefore removedwithout being left on the bottom of plug-unnecessary portion 16. It issufficient to form on-wiring stopper film 13 thickly so as not to beeliminated even by planarization of the top face of conductive layer 22(refer to FIG. 6) and removal of conductive layer 22 in plug unnecessaryportions 16 (refer to FIG. 10).

[0087] As shown in FIG. 11, resist film 15 is removed. As shown in FIG.12, insulating interlayer 6 is formed so as to cover the entire face byCVD or the like. The top face of insulating interlayer 6 is planarizedby CMP, etch back, or the like. In such a manner, the next wiring layercan be formed on the top face of insulating interlayer 6.

[0088] By repeating such a process, a semiconductor device in which aplurality of wiring layers are stacked and are connected to each othervia plugs in the vertical direction is obtained.

[0089] The semiconductor device in the embodiment has a structure asshown in FIG. 12. Specifically, when the state after insulatinginterlayer 6 is removed is assumed, wiring swellings 41 extend linearlyon the surface of semiconductor substrate 2 and a recess is created inthe main surface by being sandwiched by wiring swellings 41. In planview, plural plugs 11 are formed by a conductive material so as to burya part of the recess. The top face of wiring swelling 41 and that ofplug 11 are almost flush with each other with reference to the mainsurface as a reference. In practice, the upper side of the structure iscovered with insulating interlayer 6.

[0090] By forming insulating interlayer 6 after forming side wall spacer5 having a slope, the burying operation with insulating interlayer 6 isfacilitated, and cavities 33 (refer to FIG. 46) or the like which aregenerated in the case where the burying property is insufficient do notoccur.

[0091] Since plugs 11 are formed before insulating interlayer 6, even ifthe burying property of insulating interlayer 6 is poor and cavities 33or the like are generated, a problem such as short-circuiting by thematerial of plug 11 does not occur.

[0092] Further, since connection holes for plugs 11 are formed in aself-aligned manner before insulating interlayer 6, the number of timesside wall spacer 5 is subjected to etching decreases, so that thereduction amount of side wall spacer 5 is decreased. Wiring layer 4 andplug 11 are insulated from each other by side wall spacer 5 withreliability.

[0093] Since the burying property and insulating property are determinedonly by variations in film thickness of side wall spacer 5 without beinginfluenced by variations in film thickness of on-wiring stopper film 13and insulating interlayer 6, stable mass production can be realized.

[0094] Further, in the conventional technique, two insulatinginterlayers 6 and 106 are necessary as shown in FIG. 45, so that thedevice as a whole is thick. In contrast, in the embodiment, onlyinsulating interlayer 6 is sufficient, so that the thickness as a wholecan be reduced. Accordingly, the fabricating process can be alsosimplified.

[0095] Second Embodiment

[0096] Referring to FIGS. 13 to 18, the method of fabricating asemiconductor device according to a second embodiment of the inventionwill be described.

[0097] In the first embodiment, as a photolithographic pattern forleaving the portions corresponding to plugs, photolithographic pattern14 a (refer to FIG. 8) having the shape corresponding to each of plugsis adopted. In the second embodiment, as shown in FIG. 13, aphotolithographic pattern 14 b having a shape covering a plurality ofneighboring plugs is used. A collection of a plurality of plugs arrangedclose to each other will be called a “plug arrangement area”hereinbelow. Photolithographic pattern 14 b having a shape in theembodiment covers one plug arrangement area. In the example, acollection of three plugs formed in an active area 8 which is continuousbefore formation of wiring layer 4 and the like, that is, a collectionof three plugs for two transistors commonly using one source area fromboth sides is called a plug arrangement area. One plug arrangement areais not limited to a continuous active area. One plug arrangement areaincludes three plugs or may include the other number of plugs.

[0098]FIG. 13 corresponds to the stage of FIG. 8 in the firstembodiment. The process up to here is similar to that in the firstembodiment. Specifically, at the stage of FIG. 13, the entire top faceis covered with resist film 15. Dry etching is performed by using resistfilm 15 remained as a result of exposure with photolithographic pattern14 b, as a mask to remove conductive layer 22 in plug-unnecessaryportion 16. FIG. 14 is a plan view showing the state. FIG. 15 is a crosssection taken along line XV-XV of FIG. 14. Although on-wiring stopperfilm 13, side wall spacer 5, and isolated insulating film 1 around plugunnecessary portion 16 are slightly removed from their top faces, asdescribed above, the material has the etching rate sufficiently low ascompared with conductive layer 22, so that the removal amount does notbecome an issue. By setting etching time to be slightly long, conductivelayer 22 can be removed without being left on the bottom ofplug-unnecessary portion 16. It is sufficient to form on-wiring stopperfilm 13 thickly so as not to be eliminated even by planarization of thetop face of conductive layer 22 and removal of conductive layer 22 inplug-unnecessary portions 16.

[0099] As shown in FIGS. 16 and 17, resist film 15 is removed. In thiscase, in each plug arrangement area, wiring swelling 41 in the portionsandwiched by plugs 11 is covered with resist film 15 formed by usingphotolithographic pattern 14 b. The other portion in the linearlyextended wiring swelling 41 is not covered with resist film 15, so thatthe level of the top face of wiring swelling 41 in the portionsandwiched by plugs 11 is higher than that the top face of wiringswelling 41 in the other portion.

[0100] As shown in FIG. 18, insulating interlayer 6 is formed so as tocover the whole face by CVD or the like. The following process issimilar to that described in the first embodiment.

[0101] As described above, by using the photolithographic pattern havinga shape covering a plug arrangement area, the pattern of resist film canbe simplified, and the device can be easily formed with high accuracy.

[0102] Third Embodiment

[0103] Referring to FIGS. 19 to 24, a method of fabricating asemiconductor device according to a third embodiment of the inventionwill be described. In the second embodiment, one plug arrangement areais constructed by a collection of three plugs formed in a single activearea 8, that is, a collection of three plugs for two transistorscommonly using one source area from both sides. In the third embodiment,as shown in FIG. 19, regardless of whether the active area is continuousor not, an area including plugs arranged on a straight lineperpendicular to the extending direction of wiring layer 4 as one plugarrangement area. A photolithographic pattern 14 c covering all theplugs on the straight line is therefore adopted. In this case, in orderto avoid undesired conduction between a plug arrangement area and theother neighboring plug arrangement area, in the plug arrangement area,preferably, a notch 24 is formed in a portion close to a projection 23of the neighboring plug arrangement area so as to keep a certaindistance between the areas. By using resist film 15 remained afterperforming exposure with photolithographic pattern 14 c, dry etching isperformed. Consequently, conductive layer 22 in the portion which is notcovered with resist film 15 is removed. FIG. 20 is a plan view showingthe state. FIG. 21 is a cross section taken along line XXI-XXI of FIG.20. On-wiring stopper film 13, side wall spacer 5, and isolatedinsulating film 1 in the portion which is not covered with resist film15 are slightly removed from their top surfaces in a manner similar tothe second embodiment. In the third embodiment, there is a portion inplug unnecessary portion, which is covered with resist film, and a plugis formed also in such a portion. The plug has a shape similar to thatof plug 11 but is a dummy plug 18 having no function of the plug.However, since the lower end of dummy plug 18 is connected only toisolated insulating film 1, it is not electrically connected tosomewhere. Consequently, even when dummy plug 18 exists, there is noharm.

[0104] As shown in FIG. 22 and 23, resist film 15 is removed. FIG. 23 isa cross section taken along line XXIII-XXIII of FIG. 22. A stepgenerated in the top face of wiring swelling 41 is similar to thatdescribed in the second embodiment. As shown in FIG. 24, insulatinginterlayer 6 is formed so as to cover the entire surface by CVD or thelike. The following process is similar to that in the first embodiment.In this case, also in the final structure, dummy plug 18 remains as aplug-shaped portion directly connected only to isolated insulating film1.

[0105] As described above, by using the photolithographic pattern havinga shape covering all plugs arranged in a straight line as a plugarrangement area, the pattern of a resist film can be further simplifiedand can be easily formed with high accuracy. In the embodiment, althoughdummy plug 18 is formed also in a portion where no plug 11 is necessary,dummy plug 18 of the same material and the same shape as plug 11 isformed so as to bury a portion where plug 11 is not inherently formed.Consequently, the flatness of the top face after formation of insulatinginterlayer 6 can be increased.

[0106] Fourth Embodiment

[0107] Referring to FIGS. 25 to 30, a method of fabricating asemiconductor device according to a fourth embodiment of the inventionwill be described.

[0108] In the first to third embodiments, the invention relates toexamples characterized by the layer including plugs 11 directlyconnected to active area 21 of semiconductor substrate 2, As the fourthembodiment, the invention relates to an example characterized by a layerincluding plugs connected to a conductive area in the relatively nextlower layer in a stacked structure of one or more layers onsemiconductor substrate 2.

[0109] As shown in FIG. 25, the structure including wiring layer 4 isformed on a lower wiring layer 28 via insulating interlayer 6. Lowerwiring layer 28 includes a conductive area 31 and a non-conductive area32. Lower wiring layer 28 may be the layer formed in the first to thirdembodiments. In this case, conductive area 31 corresponds to plug 11.FIG. 25 is a cross section showing a stage corresponding to FIG. 3 ofthe first embodiment. Wiring layer 4 is formed on insulating interlayer6 and is covered with on-wiring stopper film 13. On-wiring stopper film13 is further covered with a nitride film 35. On-wiring stopper layer 13is formed thicker as compared with FIG. 3 so that, since etching isperformed longer to form a deeper connection hole 10 in the followingprocess (refer to FIG. 26), wiring layer 4 is not exposed even by theetching.

[0110] As shown in FIG. 26, the entire face is subjected to anisotropicdry etching to form connection hole 10 reaching lower wiring layer 28.Connection holes 10 are formed in a self-aligned manner. A part ofnitride film 35 remains and serves as side wall spacer 5. A portionincluding wiring layer 4, on-wiring stopper film 13, side wall spacer 5,and insulating interlayer 6, which is swollen linearly in the directionperpendicular to the drawing sheet of FIG. 26 is a wiring swelling 42.

[0111] As shown in FIG. 27, conductive layer 22 is formed in a portionsandwiched by wiring swellings 42. The method of forming conductivelayer 22 is the same as that described with reference to FIGS. 5 and 6in the first embodiment. As a result, the top face of on-wiring stopperfilm 13 and that of the remaining portion of conductive layer 22 becomealmost flat and flush with each other.

[0112] In a manner similar to the first to third embodiments, afterapplying resist film 15 on the entire face, exposure is performed with aphotolithographic pattern. As in the first embodiment, an example ofusing the photolithographic pattern covering each portion in which aplug is to be formed will be described. Therefore, resist film 15 onlyin the portion where a connection hole is desired to be formed remains,and resist film 15 in the other portion is removed. Further, while usingresist film 15 as a mask, dry etching is performed to thereby eliminateconductive layer 22 in plug unnecessary portions 16. Only the portionunder resist film 15 in conductive layer 22 remains and becomes plug 11.

[0113] As shown in FIG. 29, resist film 15 is removed. As shown in FIG.30, insulating interlayer 12 is formed so as to cover the whole face byCVD or the like. Insulating interlayer 12 is planarized by CMP, etchback, or the like. Consequently, the next wiring layer can be formed oninsulating interlayer 12.

[0114] By repeating such a process, a semiconductor device in which aplurality of wiring layers are stacked and connected to each other via aplug in the vertical direction is obtained.

[0115] Referring to FIGS. 31 to 33, another example in the embodimentwill be described. In the above-described example, the photolithographicpattern having the shape covering each portion where a plug is to beformed is used. As used in the third embodiment, a photolithographicpattern having a shape which extends linearly so as to cross a pluralityof areas in which plugs are to be formed may be used. In this case, at astage after dry etching is carried out by using resist film 15 as amask, that is, a stage corresponding to FIG. 28, as shown in FIG. 31,not only plugs 11 inherently necessary but also dummy plug 18 areformed. Since the lower end of each dummy plug 18 is connected only tonon-conductive area 32 in lower wiring layer 28, it is not electricallyconnected to somewhere and does not cause a problem even when it exists.

[0116] As shown in FIG. 32, resist film 15 is removed. As shown in FIG.33, insulating interlayer 12 is formed so as to cover the entire surfaceby CVD or the like. The following process is similar to that in thefirst embodiment. In this case, also in a final product, dummy plug 18remains as a plug-shaped portion directly connected only tonon-conductive area 32 in lower wiring layer 28.

[0117] Although the structure of a memory cell of a DRAM (Dynamic RandomAccess Memory) has been shown as an example in each of the foregoingembodiments, the invention can be applied to other semiconductor deviceseach using a self-aligned structure, such as SRAM (Static Random AccessMemory) and ROM (Read Only Memory). The invention may be applied to acircuit other than a memory cell.

[0118] According to the invention, since a fabricating method in whichplugs are formed first and an insulating interlayer is formed next canbe used, the problem of short-circuit between plugs caused by a cavitywhich is conventionally generated in the insulating interlayer can besolved. Since the number of times the side wall space is subjected toetching decreases, insulation of the wiring layer by the side wallspacer becomes more reliable. Further, the plugs have the height aboutthe same as that of the wiring swelling, so that the thickness as awhole can be reduced.

[0119] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a base layerhaving a main surface; a plurality of wiring swellings formed so as tobe linearly swollen on said main surface; and a plurality of plugs madeof a conductive material formed so as to bury a part of a recess in planview, the recess formed on said main surface by being sandwiched by saidwiring swellings, said wiring swelling including a wiring layer, awiring layer top face protective layer formed so as to cover the topface of the wiring layer, and a side wall spacer covering a side face ofsaid wiring layer and a side face of said wiring layer top faceprotective layer, and the level of the top face of said wiring swellingand that of the top face of said plug being almost the same with respectto said main surface as a reference.
 2. The semiconductor deviceaccording to claim 1, further comprising a plug arrangement area inwhich at least three plugs are arranged in the direction intersectingsaid wiring swelling, wherein in said plug arrangement area, the levelof the top face of said wiring swelling in a portion sandwiched by saidplugs is higher than that of the top face of the other portion in saidwiring swelling.
 3. The semiconductor device according to claim 2,further comprising a plug arrangement area in which at least four plugsare arranged in the direction intersecting said wiring swelling, whereinsaid base layer is a semiconductor substrate partly having an isolatedinsulating film in said main surface, and a plug directly connected onlyto said isolated insulating film in said base layer is included in saidplug arrangement area.
 4. The semiconductor device according to claim 2,further comprising a plug arrangement area in which at least four plugsare arranged in the direction intersecting said wiring swelling, whereinsaid wiring swelling includes an insulating interlayer under said wiringlayer, said base layer includes a conductive area and a non-conductivearea in plan view, and a plug directly connected only to saidnon-conductive area in said base layer is included in said plugarrangement area.
 5. A semiconductor device comprising: a base layerhaving a main surface; a plurality of wiring swellings formed so as tobe linearly swollen on said main surface; and a plurality of plugs madeof a conductive material formed so as to bury a part of a recess in planview, the recess formed on said main surface by being sandwiched by saidwiring swellings, said wiring swelling including a wiring layer, awiring layer top face protective layer formed so as to cover the topface of the wiring layer, and a side wall spacer covering a side face ofsaid wiring layer and a side face of said wiring layer top faceprotective layer, a plug arrangement area being provided in which atleast three plugs are arranged in a direction intersecting said wiringswelling, and the level of the top face of said wiring swelling in theportion sandwiched by plugs in said plug arrangement area being higherthan that of the top face of the other portion of said wiring swelling.6. The semiconductor device according to claim 5, further comprising aplug arrangement area in which at least four plugs are arranged in thedirection intersecting said wiring swelling, wherein said base layer isa semiconductor substrate partly having an isolated insulating film insaid main surface, and a plug directly connected only to said isolatedinsulating film in said base layer is included in said plug arrangementarea.
 7. The semiconductor device according to claim 5, furthercomprising a plug arrangement area in which at least four plugs arearranged in the direction intersecting said wiring swelling, whereinsaid wiring swelling includes an insulating interlayer under said wiringlayer, said base layer includes a conductive area and a non-conductivearea in plan view, and a plug directly connected only to saidnon-conductive area in said base layer is included in said plugarrangement area.
 8. A method of fabricating a semiconductor device,comprising: a wiring swelling forming step of forming a plurality ofwiring swellings on a base layer having a main surface so as to belinearly swollen on said main surface; a conducting material fillingstep of filling a recess created in said main surface by beingsandwiched by said wiring swellings with a conductive material so as tolinearly bury the recess; and a plug forming step of removing saidconductive material except for an area which becomes a plug.
 9. Themethod of fabricating a semiconductor device according to claim 8,wherein said plug forming step includes: a resist applying step offorming a resist film on the entire top face of said wiring swelling andsaid conductive material; a resist pattern forming step of forming aresist pattern by removing an unnecessary portion from said resist filmby a mask pattern covering a desired area in which a plug is to beformed; and a conductive material removing step of removing saidconductive material by using said resist pattern as a mask.
 10. Themethod of fabricating a semiconductor device according to claim 9,wherein said mask pattern has a pattern shape covering at least threedesired areas arranged in a direction intersecting said wiring swelling.11. The method of fabricating a semiconductor device according to claim10, wherein said mask pattern has a pattern shape covering said four ormore desired areas arranged in the direction intersecting said wiringswelling.